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Wolley Inc., a company specializing in high-performance data storage interfaces and controllers based in Silicon Valley, has announced the formation of its CXL Design and Integration Services Group. This group will focus on the implementation of ASIC and FPGA for data center and AI/ML computational applications.

Leveraging their in-house developed and PCI-SIG 5.0-certified CXL controller IP core, the CXL Design and Integration Services Group will provide comprehensive design and integration services for Compute Express Link (CXL) projects, including architecture design, circuit design, verification, firmware and RTL.

By utilizing these end-to-end integration services for CXL-related ASIC or FPGA implementations, customers can concentrate on exploring new architectural and system-level innovations made possible by CXL's capabilities. CXL enables customers to enhance scalability, optimize data flow with switching and fabric capabilities, streamline peer-to-peer communications and maximize resource sharing across multiple compute domains. This also allows customers to bring unique solutions to enterprise or multi-tenant server platforms.

To showcase their design and integration expertise, Wolley will host a live demo of a 4-port CXL switch implemented on a Xilinx vu19p FPGA platform at the Flash Memory Summit (FMS). This CXL switch will connect two commercially available CXL 1.1 servers with a Wolley CXL 2.0 Multiple Logic Device (MLD) end-point device implemented on a Xilinx vu13p FPGA.

Additionally, Wolley will present a paper titled "Making the Case for CXL Native Memory" at FMS, which explores an innovative idea to extend the benefits of CXL from high-performance computing to low-power mobile memory applications.

President and Founder of Wolley, Dr. Bernard Shung, stated that their engineering team has been developing the CXL/PCIe IP since 2019 and successfully obtained the PCI-SIG 5.0 certification earlier in 2023. Wolley has partnered with a tier-one high-speed interface IP provider since 2022 to offer complete CXL/PCIe solutions. Wolley's controller IP core supports up to CXL 3.0 and PCIe Gen6 x16, along with IDE capability through a separate CXL/PCIe IDE IP. The controller IP has been validated on both the Xilinx UltraScale+ FPGA platform and the Xilinx Versal FPGA platform.

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